1. Field of Invention
The present invention relates to a clock recovery circuit. More particularly, the present invention relates to a clock recovery circuit comprising a delay locked loop (DLL).
2. Description of Related Art
In a liquid crystal display device having an architecture of series-connected source drivers, after being output from a timing controller, signals of data and clock are transmitted from the first source driver to the last one in sequence in a series-connected way.
However, after signals of data and clocks pass through a logic circuit in the source driver, the duty cycle of an input signal having a primary duty cycle of 50% is changed after the input signal has passed through several stages of source drivers one after another due to an asymmetry in the speeds of the input signal at the rising edge and falling edge of signals in the logic circuit, and additionally, because it is impossible for the transmission path of data signals and the transmission path of clock signals to be totally symmetric, when a latter source driver receives an output signal from the one of the previous stages, both the setup time and hold time of the data will change significantly compared with the output of the timing controller, which therefore results in an error of data latch. This situation becomes more and more obvious as the number of the series-connected source drivers increases.
In order to solve this problem, U.S. Pat. No. 6,862,015 provides a clock recovery circuit comprising a phase locked loop (PLL) or a delay locked loop in source drivers. After the duty cycle is adjusted, data signals are output after being synchronized by clock signals such that all signals received by each of the source drivers are synchronized by the previous stage, and therefore the number of the series-connected source drivers may not be limited.
However, although the above problem is solved, a problem of harmonic lock as described in U.S. Pat. No. 5,663,665 still exists in this kind of clock recovery circuit.